A memory cell similar to the cell of the present invention is the "AST" (asymmetrical stacked trench capacitor) cell, which is discussed in "Semiconductor World", July 1991, on pages 77-82. This AST cell will be briefly described below with reference to FIGS. 1 and 3.
Referring to FIG. 3, as shown in FIG. 3a, field oxide layer 5 including portion 8 is formed by applying a planar method in order to isolate certain elements, silicon nitride layer 6 is deposited thereon, and then trench 2 with a depth of 3.5 micrometers is formed. Then oxide layer 9 of 50 nanometers thickness is formed within the trench, and photoresist 7 is coated thereon and patterned by a photolithographic process.
Then, relevant portions of oxide layer 9 are etched using photoresist pattern 7 and silicon nitride layer 6 formed on the silicon substrate as a mask, thereby forming a contact portion for a storage electrode of a storage capacitor.
Then, as shown in FIG. 3b, nitride layer 6 and photoresist 7 (used as a mask) are removed, and polysilicon 12 is deposited so that the polysilicon serves as the storage electrode. Then an "As" ion implantation is carried out, and polysilicon 12 is patterned to form a capacitor electrode.
Then, as shown in FIG. 3c, NO layer 14 (nitride-oxide, Si.sub.3 N.sub.4 -SiO.sub.2) as a dielectric medium of the capacitor is deposited on polysilicon storage electrode 12 of the capacitor, and polysilicon is deposited and patterned to form plate electrode 15 of the storage capacitor, thereby completing formation of the capacitor.
FIG. 1 illustrates the layout of the AST cell formed in the above described manner.
In this AST cell, trench 2, wherein the capacitor is formed, is arranged in an asymmetrical manner relative to active region 1 of the device, and, therefore, contact 120 of storage electrode 12 is completely included within active region 1, while the capacitor is electrically isolated from the substrate by oxide layer 9 which is formed within trench 2. Owing to the asymmetrical arrangement of trench 2, a distance is secured between contact 120 of storage electrode 12 and a nearby element. Further, owing to the existence of the oxide layer which is formed on the inner wall of the trench, leakage currents can be decreased between adjacent trenches, thereby making it possible to obtain a fine structure.
However, as shown in FIG. 1, if the minimum distance between the trenches, the shorter width of the active region and the minimum width of a design rule are represented by "d", there exists a distance "a" between capacitor electrode contact 120 and word line 3, and a distance "b" between the trench and the corner of the active region.
Therefore, the minimum pitch P.sub.W and the length of the active region are larger than 2.times.d and 3.times.d, respectively, and therefore, there is a limit to achieving a memory cell with a fine structure.
Further, when forming the capacitor electrode contact, a photoresist is used, and consequently variations in contact resistance may occur due to alignment errors.